Development of a Readout System for a High Rate Micron Resolution Single Photon UV Imaging Detector.

Abstract

Ultraviolet (UV) photon detection in astronomical applications requires detectors capable of single photon counting at Megahertz event rates with high spatial resolution and very low noise. NASA, through their Strategic Astrophysics Technology (SAT) program, has funded the development of a cross strip (XS) microchannel plate (MCP) detector along with the corresponding read-out electron- ics with the intention to increase its technology readiness level (TRL), thus enabling prototyping of such systems/detectors for future NASA missions. The detectors designed for measuring low intensity light (single photons) must be robust against

uctuating count rates, have very good spatial resolution (μm range), and contribute very low back- ground noise to the image. These requirements lead toward the development of custom Application Speci c Integrated Circuits (ASICs), which are able to read the signals from the detector, while contributing a minimal amount of noise to the system. The readout system described in this work has been designed with the intent to replace the original 19-inch rack-mounted, high-powered electronics with ASICs in order to lower the power, mass, and volume requirements of the detec- tor electronics, which are all very limited resources in space applications. Thus a collaboration between the Space Science Laboratory at University of Berkeley and the Instrumentation Devel- opment Laboratory (IDLab) at the University of Hawaii at Manoa has been established, in which IDLab is responsible for the development of the read-out electronics. This thesis presents the design, fabrication, and testing of the ASICs required for the readout system. In the rst phase, a 16-channel trans-impedance ampli er ASIC (CSAv3) was designed and developed; this component converts the collected charge from the detector into a measur- able voltage pulse. These pulses are subsequently transferred upon and digitized by a waveform sampling ASIC (HalfGraph2). The post processing of the acquired information is done on eld programmable gate arrays (FPGAs) and the results are transferred to a computer for analysis. After successfully completing the rst phase, the second phase is to further integrate the readout system by combining the CSAv3 and HG2 chips into one high-density, low power, front-end mixed- signal ampli er/digitizing ASIC, denoted as GRAPH, with further improvements to the design of the individual parts to decrease the material budget, lower the power consumption, improve the performance, and ultimately reduce the physical footprint of the electronics.