Hong, Yun-Pyo2011-07-212011-07-212008http://hdl.handle.net/10125/20573Thesis (M.S.)--University of Hawaii at Manoa, 2008.Includes bibliographical references (leaves 84-85).xii, 85 leaves, bound ill. 29 cmIn this thesis work, three double balanced resistive mixers realized in a 0.25 Ii m CMOS TSMC process were designed and fabricated in order to obtain low conversion loss and high input third order intercept point(IIP3), and in order to compare the flicker noise of NMOSFET to PMOSFET. These mixers were designed for wireless applications with RF and IF frequency ranges of I to 3 GHz, and DC to 50 MHz, respectively. The mixer design process as well as simulated and measured results are given and discussed. A measured conversion loss of 10.1 dB, 21.8 dB and 14.8 dB of NMOSFET and PMOSFET mixers has been achieved respectively. Measured linearity values are 7 dBm, 17 dBm and 14 dBm for 1dB compression point and 12 dBm, 7 dBm and 19.25 dBm for third order intercept point. All measured isolation values are higher than 45 dB between all ports. The circuit was simulated using Agilent ADS software with BSIM3v3 transistor models and the layout has been carried out in Cadence. These mixers achieve a broadband performance, at moderate conversion loss.en-USAll UHM dissertations and theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission from the copyright owner.Thesis