Readout methods for high rate binary pixel detectors in silicon on insulator technology

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University of Hawaii at Manoa

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The SuperKEKB accelerator will have an order of magnitude more luminosity than the world record luminosity of the KEKB accelerator. In order to cope with the increased signal background and high occupancy rates in the Belle II detector, the Silicon Vertex Detector (SVD) will be augmented with layers of Pixel Detectors (PXDs). This dissertation focuses on the design of two new readout methods for binary PXDs for vertexing applications in lepton colliding experiments. Such experiments include the Belle II and the International Linear Collider (ILC). The binary readout methods described herein are made possible by the use of a 0.20μm Silicon On Insulator (SOI) manufacturing process. The SOI process is undergoing research by a worldwide collaboration to investigate SOI for use in SVD applications. The first readout method presented here uses a two-bit binary output that time-encodes the pixel hit information by means of a signal shifting mechanism. The hit re-construction, background rate, detector occupancy, and data volume are described. Particular interest is for use in the high luminosity environment of the under-construction SuperKEKB accelerator. Our results from the CAP11 ASIC, using the two-bit binary read-out method, are presented. The second readout method presented is the Hixel readout method. The Hixel uses a similar time-encoding signal shifting mechanism to the binary readout method. Three bits of hit information and dedicated shift stages at the detector periphery are unique characteristics. The periphery shift stages allow for more compact pixels and enable higher shifting frequencies, reducing reconstruction ambiguities. The Hixel method is shown to greatly reduce device occupancy and the volume of data generated with the use of multiple signal transfer lines. Two ASICs were fabricated using our design implementing the Hixel readout method: the CAP9 and CAP12. Test results from both ASICs are presented. Particular attention is paid to the analog performance.

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Theses for the degree of Doctor of Philosophy (University of Hawaii at Manoa). Electrical Engineering.

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