Verification of a Transport Offload Engine
| dc.contributor.advisor | Reed, Todd R | |
| dc.contributor.author | Raut, Abhay | |
| dc.contributor.department | Electrical Engineering | |
| dc.date.accessioned | 2009-03-06T19:32:08Z | |
| dc.date.available | 2009-03-06T19:32:08Z | |
| dc.date.graduated | 2002-12 | |
| dc.date.issued | 2002-12 | |
| dc.description.abstract | Technological advances have strong impact on the integrated circuit (IC) complexity and size. Traditional methods used for verification of digital designs have difficulties to handle this growth. It is thus necessary to develop efficient methodologies for designing verification environments. A C++ based verification environment allows reducing the verification effort and contributes to raise the level of abstraction at which testbenches are described. This thesis describes a C++ based verification environment called ""CPeer"" that was developed to verify the functionality of a Transport Offload Engine (TOE). A TOE is one of the technologies that offload the TCP/IP processing from the host processor to the host bus adapter or network interface card thereby reducing the server-networking bottleneck. | |
| dc.description.degree | M.S. | |
| dc.format.extent | x, 85 pages | |
| dc.identifier.uri | http://hdl.handle.net/10125/6959 | |
| dc.language | eng | |
| dc.publisher | University of Hawaii at Manoa | |
| dc.relation | Theses for the degree of Master of Science (University of Hawaii at Manoa). Electrical Engineering; no. 3756 | |
| dc.rights | All UHM dissertations and theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission from the copyright owner. | |
| dc.rights.uri | https://scholarspace.manoa.hawaii.edu/handle/10125/2047 | |
| dc.title | Verification of a Transport Offload Engine | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| local.identifier.callnumber | Q111 .H3 no. 3756 | |
| local.thesis.degreelevel | MS |
