Readout methods for high rate binary pixel detectors in silicon on insulator technology

Abstract

The doubling of the beam currents and more than an order of magnitude increase in luminosity requires significant upgrades to the Belle detector. The Belle2 detector design has required the inner layer of the SVD to move half as close to the beam pipe as in the Belle detector while reducing the occupancy. The SVD technology from Belle would be unable to reconstruct the vertex due to high occupancy rates. The increased luminosity will yield data rates too high for storage and processing. To cope with the accelerator and Belle2 design requirements, the objective of this project is four-fold: Develop a PXD for the Belle2 SVD Explore Time-Encoding Signal Shifting Readout Reduce occupancy compared to the Belle SVD Reduce data output compared to the Belle SVD